The present invention relates to a continuous counting device which continuously repeats counting of input signal pulses incoming at irregular intervals in a predetermined counting period.
FIG. 1 is a block diagram showing, by way of example, the arrangement of a conventional counting circuit. When supplied with a reference clock from a reference clock source 11, a gate control circuit 12 frequency divides the reference clock and provides a gate signal B of a predetermined length to one input terminal of an AND gate 13. Input signal pulses C to be counted are applied to the other input terminal of the AND gate 13. While being supplied with the gate signal B from the gate control circuit 12, the AND gate 13 provides at its output terminal input signal pulses D to be counted, which are applied to a clock input terminal T of a counter 14. The counter 14 counts the input signal pulses D and, at the same time, provides the count value to a temporary storage register 15.
Having completed frequency dividing a predetermined number of reference clocks, the gate control circuit 12 stops outputting the gate signal B. Consequently, the AND gate 13 is disabled, cutting off the supply of the input signal pulses C to the counter 14. The gate signal B is applied to an end pulse generator 16 as well. Upon discontinuation of the supply of the gate signal B, the end pulse generator 16 generates and applies an end pulse E to the temporary storage register 15 and a reset pulse generator 17. By the leading edge of the end pulse E the temporary storage register 15 inputs thereinto the current count value output of the counter 14 and provides it to a display 18 for display thereon. On the other hand, the reset pulse generator 17 yields a reset pulse A at the timing of the trailing edge of the end pulse E and provides it to the gate control circuit 12 and the counter 14. When supplied with the reset pulse A, the counter 14 is cleared to zero and the gate control circuit 12 is reset to its initial state for the frequency dividing operation. That is to say, the control circuit 12 resumes the outputting of the gate signal B and newly starts the frequency dividing of the reference clock. Upon completion of the predetermined frequency dividing operation, the gate signal B is made low-level. By repeating the above operation input signal pulses incoming in the counting period are counted and the count value is displayed.
FIG. 2 shows a series of waveforms, for explaining an example of the operation of the counting device depicted in FIG. 1.
When supplied with the reset pulse (A- .circle.1 ) from the reset pulse generator 17, the gate control circuit 12 provides the gate signal B (B- .circle.1 ) and, at the same time, starts the frequency division of the reference clock (not shown in FIG. 2). While being supplied with the gate signal B (B- .circle.2 ), the AND gate 13 outputs at its output terminal the input signal pulses C applied to the other input terminal and applies them as pulses D to the counter 14. The counter 14 counts the supplied signal pulses D.
When the gate control circuit 12 completes the frequency dividing operation and stops the generation of the gate signal B- .circle.3 ), the end pulse generator 16 immediately generates the end pulse E (E- .circle.1 ). By the leading edge of the end pulse E the count value of the counter 14 is read into the temporary storage register 15, through which it is provided to the display 18 for display thereon as display F. On the other hand, the reset pulse generator 17 generates the reset pulse A (A- .circle.2 ) by the trailing edge of the end pulse E. The reset pulse A clears the counter 14 to zero and causes the gate control circuit 12 to re-supply the gate signal B (B- .circle.4 ) to the AND gate 13.
As described above, according to the conventional counting device, the period during which the frequency-divided output of the gate control circuit 12, that is, the gate signal is output therefrom is the counting operation period of the counter 14, during which input signal pulses supplied thereto via the AND gate 13 are counted and which is followed by the display operation period in which the count value N1 obtained in the counting period is read into the temporary storage register 15 and is then displayed on the display. Then, in the next subsequent counting operation period input signal pulses are counted again and the count value N2 obtained in the counting operation period is displayed in the next subsequent display operation period.
As will be appreciated from the above, according to the prior art counting device, the counting operation period is predetermined, the input signal pulses incoming in the counting operation period are counted, and upon completion of the counting period, the display period is initiated in which to display the count value obtained in the counting period, followed by the next counting period for newly counting input signal pulses. Accordingly, no count is taken of the number of input signal pulses which are applied in the time interval occurring between individual counting operation periods, that is, during the display operation period, thus resulting in discontinuous countings.
For example, where an input signal pulse of a particularly low frequency of occurrence happens to be applied in the display operation period, such a rare incoming pulse cannot be seized and an opportunity of collecting such valuable data is lost; accordingly, it is impossible to obtain an accurate continuous count value of data.